The present invention relates to a semiconductor device fabrication technique, more specifically a semiconductor device having DRAM-type memory elements, and a method for fabricating the same.
A DRAM is a semiconductor memory device which can be formed of memory cells each having one transistor and one capacitor. Various structures and fabrication methods have been conventionally studied for semiconductor memory devices of higher density and higher integration. Especially a structure of the capacitors of DRAM much influences the integration, and it is significant how to ensure a required storage capacitance without preventing higher integration of the device.
A conventional method for fabricating a DRAM-type semiconductor device will be explained with reference to FIGS. 32A-32B, 33A-33B, 34A-34B, and 35A-35B. FIGS. 32A-32B, 33A-33B, 34A-34B, and 35A-35B are sectional views of the semiconductor device in the steps of the method for fabricating the same.
First, in the same way as in the usual method for fabricating a MOS transistor, a memory cell transistor including a gate electrode 102 and source/drain diffused layers 104, 106, and a peripheral circuit transistor including a gate electrode 108 and a source/drain diffused layer 110 are formed on a silicon substrate 100.
Next, a bit line 114 and an interconnection layer 116 are formed on an inter-layer insulation film 118 covering the memory cell transistor and the peripheral circuit transistor, electrically connected respectively to the source/drain diffused layer 104 through a plug 112, and to the gate electrode 108 or to the source/drain diffused layer 110.
Then, an inter-layer insulation film 120 is formed on the inter-layer insulation film 118, on which the bit line 114 and the interconnection layer 116 are formed.
Next, a plug 124 is buried in the inter-layer insulation films 120, 118, electrically connected to the source/drain diffused layer 106 through a plug 122 (FIG. 32A).
Then, on the inter-layer insulation film 120 with the plug 124 buried in, an etching stopper film 126 of a silicon nitride film, an inter-layer insulation film 128 of a silicon oxide film, and a mask film 130 of an amorphous silicon film are formed by, e.g., CVD method.
Then, the mask film 130, the inter-layer insulation film 128 and the etching stopper film 126 are patterned by the lithography and etching to form an opening 132 which arrives at the plug 124 (FIG. 32B).
A conducting film 134, such as a Ru (Ruthenium) film, SRO (SrRuO3) film or others, is formed on the entire surface by, e.g., CVD method.
Then, a silicon oxide film 136 is deposited on the entire surface by, e.g., CVD method and etched back by, e.g., CMP method or dry etching to fill the opening 132 with the conducting film 134 formed in by the silicon oxide film 136 (FIG. 33A).
Next, the surfaces of the conducting film 134, the silicon oxide film 136 and mask film 130 are uniformly retreated by CMP method or dry etching until the inter-layer insulation film 128 is exposed. Thus, a cylindrical storage electrode 138 of the conducting film 134 is formed in the opening 132 (FIG. 33B).
Then, the silicon oxide film 136 and the inter-layer insulation film 128 are selectively etched with the etching stopper film 126 as a stopper to expose the inside and outside walls of the storage electrode (FIG. 34A).
Then, a dielectric film of, e.g., Ta2O5 film or BST film on the entire surface by, e.g., CVD method to form a capacitor dielectric film 140 of the dielectric film, covering the storage electrode 138.
Next, annealing is performed to sufficiently crystallize the capacitor dielectric film 140, and thermal oxidation is performed to supplement oxygen defects in the capacitor dielectric film 140 (FIG. 34B). Conditions for the thermal processing are different depending on dielectric materials forming the capacitor dielectric film 140, but the processing at a high temperature of 500-850xc2x0 C. is necessary.
Next, a conducting film, such as an Ru film or SRO film, is deposited on the entire surface by, e.g., CVD method and patterned to form a plate electrode 142 of the conducting film, covering the storage electrode 138 interposing the capacitor dielectric film 140 therebetween (FIG. 35A).
Thus, a capacitor including the storage electrode 138, the capacitor dielectric film 140 and the plate electrode 142 and connected electrically to the source/drain diffused layer 106 of the memory cell transistor is formed.
Next, a silicon oxide film is deposited on the entire surface by, e.g., CVD method to form an inter-layer insulation film 144 of the silicon oxide film.
Next, as required, an interconnection layer 146 and an interconnection layer 148 are formed, connected respectively to the plate electrode 142 and to the interconnection layer 116 (FIG. 35B).
Thus, a DRAM comprising memory cells each including one transistor and one capacitor is fabricated.
As described above, in the conventional semiconductor device fabrication method, crystallization of the capacitor dielectric film 140 is improved for higher dielectric constant, or for low leak current, high-temperature thermal processing is performed after the capacitor dielectric film 140 has been formed.
However, such thermal processing can improve film quality of the capacitor dielectric film 140, but on the other hand deteriorate electric characteristics between the storage electrode 138 and the plug 124.
In a case, for example, that the plug 124 is formed of doped polycrystalline silicon, a silicide layer formed in the contact region between the storage electrode 138 and the plug 124 aggregate, reducing a contact area, with a result of increase of the contact resistance. Often a dopant of the plug 124 is absorbed by the silicide layer, forming a region of a lower dopant concentration on the upper end of the plug 124, with a result of higher contact resistance.
In a case that the thermal processing in an oxidizing atmosphere is necessary, when the plug 124 is formed of doped polycrystalline silicon, or a metal, such as W (tungsten), the contact region of the plug 124 is oxidized, with a result of increased contact resistance.
In order to suppress such contact resistance increase, it is considered that a barrier metal, as of a TiN film, is formed on the top of the plug 124, but the step of forming the barrier metal must be added. Fabrication cost increase is inevitable. Depending on kinds of the storage electrode 138 and the capacitor dielectric film 140, oxidizing ability in the thermal processing is too high to select a suitable barrier metal for preventing the oxidation.
In the thermal processing, materials forming the plug 124 are diffused in the storage electrode 138 to deteriorate compatibility between the storage electrode 138 and the capacitor dielectric film 140, often with a result of decreased breakdown voltage and increased capacitor leak current.
The above-described problems will be solved by lowering crystallization annealing temperature and the thermal processing temperature for the capacitor dielectric film 140. However, the thermal processing at low temperatures is not sufficient for the crystallization and supplement of oxygen defects, with results of decreased dielectric constants of the capacitor dielectric film 140 or increased leak current. The crystallization annealing and thermal oxidation for the capacitor dielectric film 140 will have to be performed at higher temperature as the capacitor dielectric film 140 is thinner. Accordingly, also for further micronization of semiconductor devices it is required to prohibit the influence of the thermal processing.
An object of the present invention is to provide a semiconductor device and a method for fabricating the semiconductor device which can prohibit electric characteristic deterioration between the storage electrodes and the lower electrodes, etc. connected to the storage electrodes in the steps of crystallization annealing and oxidizing the capacitor dielectric film.
According to one aspect of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps of: forming a first insulation film above a substrate; forming a first opening in the first insulation film down to the substrate; forming a plate electrode on at least a side wall of the first opening; removing the first insulation film to form a second opening having a side wall surrounded by the plate electrode; forming a capacitor dielectric film on at least the side wall of the second opening; and forming a storage electrode on the capacitor dielectric film formed on the side wall of the second opening.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a storage electrode having a side wall forward tapered; a capacitor dielectric film formed on the side wall of the storage electrode; and a plate electrode formed on the side wall of the storage electrode interposing the capacitor dielectric film therebetween, the plate electrode having a side wall inversely tapered.
According to the present invention, insulation film is formed on a substrate, a first opening is formed in the insulation film down to the substrate, a plate electrode is formed on at least the side wall of the first opening, the first insulation film is removed to form a second opening having the side wall surrounded by the plate electrode, a capacitor dielectric film is formed on at least the side wall of the second opening, and a storage electrode is formed on the side wall of the second opening through the capacitor dielectric film, whereby electric characteristics between the electrode, etc. in the below structure and the storage electrode are prevented from deterioration in high-temperature thermal processing in the step of forming the capacitor dielectric film.
The thermal processing can be performed without taking into consideration electric characteristics between the lower electrode and the storage electrode, whereby the thermal processing can be performed under conditions which are optimum for the capacitor dielectric film, and the capacitor dielectric film can have higher dielectric constant and higher film quality.